View ST8012_2385606.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

st ST8012 do tmatrixlcd 120outputlcdcommon/segmentdriveric notice: sitronixtechnologycorp.reservestherig httochangethecontentsinthisdocumentwithout priornotice. thisisnotafinal specification.someparametersaresubjecttochang e. v1.6 1/47 2004/09/08 1. description the ST8012 is a 120output segment/common driver ic suitable for driving small/medium scale dot matr ix lcdpanels,andisusedinpdaorelectronicdictio nary. theST8012isgoodasasegmentdriveroracommon driveroracommon/segmentdriver,anditcancreat ea low power consuming, highresolution lcd. the ST8012haveeightmodescanselectedtosetcommon and segment numbers by select pin. the ST8012 alsohaveanalogdc/dcconvertertouse. 2. features numberoflcddriveoutputs:120 supplyvoltageforlcddrive:max+16v supplyvoltageforthelogicsystem:+2.5to+5.5 v lowpowerconsumptionandlowoutputimpedance displa yduty select able by select pin lowpowerliquidcrystaldisplaypowersupplycirc uit equippedinternally. boostercircuit(withboostratioof2x/3x/4x/5x/6x ) abundantcommandfunctions lcdbiasset,electronicvolume,v ss voltage regulationinternalresistorratioandbooster frequency. allfunctionshaveinitialvalue,usercanusethe defaultvalueorsettingbyprogrammablepintoset . ifselectsegmentmodethenexceptboostercircuit willopenedotherscircuit(followerandregulator circuit)willautomaticclosed. whendontusedtheserialinterface,wecanselec t oneofdefaultmodesbyserialinterfacepinspleas e seetable5. package:154pincob. (segment mode) shiftclockfrequency 20mhz(max.):v dd =+5.00.5v 15mhz(max.):v dd =+3.0to+4.5v 12mhz(max.):v dd =+2.5to+3.0v adoptsadatabussystem 4bitparallel/serialinputmodesareselectable witha mode(p/s)pin automatictransferfunctionofanenablesignal automaticcountingfunctionwhich,inthechip selectionmode,causestheinternalclocktobe stoppedbyautomaticallycounting88 72 56 40 24 8or120bitsofinputdata linelatchcircuitsareresetwhenxdispoffactive (common mode ) shiftclockfrequency:4mhz(max.) sel 2 ,sel 1 ,sel 0 duty bias 0 0 0 segmentmode 0 0 1 1/32 1/6or1/5 0 1 0 1/48 1/7or1/5 0 1 1 1/64 1/9or1/7 1 0 0 1/80 1/9or1/7 1 0 1 1/96 1/10or1/8 1 1 0 1/112 1/11or1/9 1 1 1 1/120 1/11or1/9
ST8012 v1.6 2/47 2004/09/08 builtinxbitshiftregister availableinasinglemode y 1 >y x singlemode y x >y 1 singlemode ps:x=32 48 64 80 96 112 120 theabove4shiftdirectionsarepinselectable shiftregistercircuitsareresetwhenxdispoff active
ST8012 v1.6 3/47 2004/09/08 3. pin description symbol i/o description noofnum comseg 0 comseg 119 o lcddriveoutput 120 v 0 ~v 4 p powersupplyforlcddrive 5 l/r i displaydatashiftdirectionselection 1 v dd p powersupplyforlogicsystem(+2.5to+5.5v) 1 eio 2 ,eio 1 i/o input/outputforchipselectionatsegmentmodeand flminputoutput functionatcom/segmixmodeorcommonmode 2 di 0 di 3 i displaydatainputatsegmentmode 4 xck i clockinputfortakingdisplaydataatsegmen tmode 1 xdispoff i controlinputforoutputofnonselectl evel 1 lp i latchpulseinputfordisplaydataatsegmentmod e/ shiftclockinputforshiftregisteratcommonmode 1 fr i acconvertingsignalinputforlcddrivewavef orm 1 xrst i systemresetpin.whenlowlevelactive. thexrstlpulsetimingminvalueis200usandmax valueis0.5s 1 p/s i thisistheparalleldatainput/serialdatainputs witchterminal. p/s=h:paralleldatainput. p/s=l:serialdatainput. 1 v ss p ground(0v) 1 cap1 o dc/dcvoltageconverter. connectacapacitorbetwee nthisterminal andthecap2terminal. 1 cap1+ o dc/dcvoltageconverter. connectacapacitorbetwee nthisterminal andthecap1terminal. 1 cap2 o dc/dcvoltageconverter. connectacapacitorbetwee nthisterminal andthecap2terminal. 1 cap2+ o dc/dcvoltageconverter. connectacapacitorbetwee nthisterminal andthecap2terminal. 1 cap3+ o dc/dcvoltageconverter . connectacapacitorbetweenthisterminal andthecap1terminal. 1 cap4+ o dc/dcvoltageconverter. connectacapacitorbetwee nthisterminal andthecap2terminal. 1 cap5+ o dc/dcvoltageconverter. connectacapacitorbetwee nthisterminal andthecap1terminal. 1 vout o dc/dcvoltageconverter. connectacapacitorbetwee nthisterminal andvss. 1 xcs i thisisthecommandmodeselectpin. whenxcs=lthenwritecommandtothelcd.seefig ure1 1
ST8012 v1.6 4/47 2004/09/08 dont toggle sclk or sid from low level while xcs sign al is hight sid i thecommanddata.seefigure1 1 sclk i theserialclockinput.seefigure1 1 sel 2 ~sel 0 i thesepinaredutyselection. sel 2 ,sel 1 ,sel 0 sel3,2,1 duty bias 0 0 0 0,0,0 segmentmode 0 0 1 0,0,1 1/32 1/6or1/5 0 1 0 0,1,0 1/48 1/7or1/5 0 1 1 0,1,1 1/64 1/9or1/7 1 0 0 1,0,0 1/80 1/9or1/7 1 0 1 1,0,1 1/96 1/10or1/8 1 1 0 1,1,0 1/112 1/11or1/9 1 1 1 1,1,1 1/120 1/11or1/9 3
ST8012 v1.6 5/47 2004/09/08 4. block diagram com/segment driver level shifter segment data latch /dispoff com/seg com/seg comseg 0 .............. v1 v3 v3 v4 vss lp command decorder voltage fallower circuit voltage regulator circuit voltage booster circuit power supply circuit vout cap1- cap1+ cap2- cap2+ cap3- cap4+ cap5+ vss com/seg data latch fr sclk sid xcs l/r eio control eio1 eio2 shift control data in control 3 sel2~sel0 4 xck p/s din 4 shift_control c d o u t c d i n di0~di3 v0 xrst comseg x
ST8012 v1.6 6/47 2004/09/08 input/output circuits i v d d t o interna lc irc u it v s s (0 v ) a p p lic ab lep in s l/r ,d i 3 ~ d i 0 , x d is p o f f ,l p ,f r ,p /s c s ,s id ,s e l 2~ s e l0 input circuit v dd i/o tointernal circuit vss(0v) vss(0v) controlsignal vss(0v) v dd outputsignal controlsignal applicationpins eio 1 ,eio 2 input/output circuit
ST8012 v1.6 7/47 2004/09/08 5. functional description 5.1 pin functions (segment mode) symbol function v dd logicsystempowersupplypin,connectedto+2.5t o+5.5v. v ss groundpin,connectedto0v. v 0 v 1 v 2 v 3 v 4 thisisamulti levelpowersupplyfortheliquidcrystaldrive.th evoltagesupplyappliedisdetermined bytheliquidcrystalcell,andischangedthrough theuseofaresistivevoltagedividedorthrough changingtheimpedanceusinganop.amp.voltagele velsaredeterminedbasedonvss,andmust maintaintherelativemagnitudesshownbelow. v 0 R v 1 R v 2 R v 3 R v 4 R v ss whenthepowersupplyturnson,theinternalpower supplycircuitsproducethev 1 tov 4 voltagesshownbelow. thevoltagesettingsareselectedusingthelcdbia ssetcommand. 1/120duty 1/112duty 1/96duty 1/80duty 1/64duty 1/ 48duty 1/30duty v 4 1/11*v0,1/9*v0 1/11*v0,1/9*v0 1/10*v0,1/8*v0 1/9*v0,1/7*v0 1/9*v0,1/7*v0 1/7*v0,1/5*v0 1/6*v0,1/5*v0 v 3 2/11*v0,1/9*v0 2/11*v0,2/9*v0 2/10*v0,2/8*v0 2/9*v0,2/7*v0 2/9*v0,2/7*v0 2/7*v0,2/5*v0 2/6*v0,2/5*v0 v 2 9/11*v0,7/9*v0 9/11*v0,7/9*v0 8/10*v0,6/8*v0 7/9*v0,5/7*v0 7/9*v0,5/7*v0 5/7*v0,3/5*v0 4/6*v0,3/5*v0 v 1 10/11*v0,8/9*v0 10/11*v0,8/9*v0 9/10*v0,7/8*v0 8/9*v0,6/7*v0 8/9*v0,6/7*v0 6/7*v0,4/5*v0 5/6*v0,4/5*v0 di 3 di 0 inputpinsfordisplaydata in4bitparallelinputmode,inputdataintothe 4pins,di 3 di 0 . inserialinputmode,inputdataintothe1pin,di 0 . connectdi 3 di 1 tov ss . referto"relationshipbetweenthedisplaydataan dlcddriveoutput pins"infunctionaloperations. xck clockinputpinfortakingdisplaydata *dataisreadatthefallingedgeoftheclockpul se. xrst systemresetpin.whenlowlevelactive. ifnotusedthehardwarereset,thispinmustpull height. thexrstlpulsetimingminvalueis200usandmax valueis0.5s lp latchpulseinputpinfordisplaydata dataislatchedatthefallingedgeoftheclockp ulse. l/r inputpinforselectingthereadingdirectionofdi splaydata whensettov ss level"l",dataisreadsequentiallyfromcomseg 119 tocomseg 0 . whensettov dd level"h",dataisreadsequentiallyfromcomseg 0 tocomseg 119 . referto"relationshipbetweenthedisplaydataan dlcddriveoutput pins"infunctionaloperations. xdispoff controlinputpinforoutputofnonselectlevel theinputsignalislevelshiftedfromlogicvolta geleveltolcddrivevoltagelevel,andcontrolst he lcddrivecircuit.
ST8012 v1.6 8/47 2004/09/08 whensettovsslevel"l",thelcddriveoutputpi ns(comseg 0 comseg 119 )aresettolevelvss. whensetto"l",thecontentsofthelinelatchar ereset,butthedisplaydataarereadinthe datalatchregardlessoftheconditionofxdispoff. whenthexdispofffunctioniscanceled, thedriveroutputsnonselectlevel(v 2 orv 3 ),thenoutputsthecontentsofthedatalatchatt henext fallingedgeofthelp.atthattime,ifxdispoffr emovaltimedoesnotcorrespond towhatisshown inaccharacteristics,itcannotoutputthereading datacorrectly. tableoftruthvaluesisshownin"truthtable"in functionaloperations. fr acsignalinputpinforlcddrivewaveform theinputsignalislevelshiftedfromlogicvolta geleveltolcddrivevoltagelevel,andcontrolst he lcddrivecircuit. normallyitinputsaframeinversionsignal. thelcddriveoutputpins'outputvoltagelevelsc anbesetusingthelinelatchoutputsignal andthe frsignal. tableoftruthvaluesisshownin"truthtable"in functionaloperations. p/s interfacemodeselectionpin whenp/sishthenparalleldatainputmode. whenp/sisltheserialdatainputmode, elo 1 ,eio 2 input/outputpinsforchipselection. atsegmentmode: whenl/rinputisatv ss level"l",elo 1 issetforoutput,andeio 2 issetforinput(connecttovss). whenl/rinputisatv dd level"h",elo 1 issetforinput(connecttovss),andeio 2 issetforoutput. duringoutput,setto"h"whilelp?xckis"h"an dafter120bitsofdatahavebeenread,set to"lforonecycle(fromfallingedgetofailing edgeofxck),afterwhichitreturnsto"h". duringinput,thechipisselectedwhileelisset to"l"afterthelpsignalisinput.thechipis nonselectedafter120bitsofdatahavebeenread. comseg 0 Ccomseg 119 lcddriveoutputpins correspondingdirectlytoeachbitofthedatalat ch,onelevel(v 0 ,v 2 ,v 3 ,v ss )isselectedandoutput. tableoftruthvaluesisshownin"truthtable"in functionaloperations. cap1 dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap2terminal. cap1+ dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap1terminal. cap2 dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap2terminal. cap2+ dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap2terminal. cap3+ dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap1terminal. cap4+ dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap2terminal. cap5+ dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap1terminal. vout dc/dcvoltageconverter.connectacapacitorb etweenthisterminalandvss. xcs this is the command mode select pin.when xcs=l t hen write command to the lcd , when not usedthecommandmodethenmustfixedtovdd.see figure1 sid thecommanddata,whennotusedthecommandmod ethenmustfixedtovdd.seefigure1 sclk theserialclockinput,whennotusedthecomm andmodethenmustfixedtovdd.seefigure1
ST8012 v1.6 9/47 2004/09/08 (common mode) symbol function v dd logicsystempowersupplypin,connectedto+2.5t o+5.5v. v ss groundpin,connectedto0v. v 0 ,v 1 v 2 ,v 3 v 4 thisisamulti levelpowersupplyfortheliquidcrystaldrive.th evoltagesupplyappliedisdetermined bytheliquidcrystalcell,andischangedthrough theuseofaresistivevoltagedividedorthrough changingtheimpedanceusinganop.amp.voltagele velsaredeterminedbasedonvdd,andmust maintaintherelativemagnitudesshownbelow. v 0 R v 1 R v 2 R v 3 R v 4 R v ss whenthepowersupplyturnson,theinternalpower supplycircuitsproducethev1tov4voltages shownbelow.thevoltagesettingsareselectedusin gthelcdbiassetcommand. 1/120duty 1/112duty 1/96duty 1/80duty 1/64duty 1/ 48duty 1/30duty v 4 1/11*v0,1/9*v0 1/11*v0,1/9*v0 1/10*v0,1/8*v0 1/9*v0,1/7*v0 1/9*v0,1/7*v0 1/7*v0,1/5*v0 1/6*v0,1/5*v0 v 3 2/11*v0,1/9*v0 2/11*v0,2/9*v0 2/10*v0,2/8*v0 2/9*v0,2/7*v0 2/9*v0,2/7*v0 2/7*v0,2/5*v0 2/6*v0,2/5*v0 v 2 9/11*v0,7/9*v0 9/11*v0,7/9*v0 8/10*v0,6/8*v0 7/9*v0,5/7*v0 7/9*v0,5/7*v0 5/7*v0,3/5*v0 4/6*v0,3/5*v0 v 1 10/11*v0,8/9*v0 10/11*v0,8/9*v0 9/10*v0,7/8*v0 8/9*v0,6/7*v0 8/9*v0,6/7*v0 6/7*v0,4/5*v0 5/6*v0,4/5*v0 lp shiftclockpulseinputpinforbidirectionalshif tregister *dataisshiftedatthefallingedgeoftheclock pulse. xrst systemresetpin.whenlowlevelactive. ifnotusedthehardwarereset,thispinmustpull height. thexrstlpulsetimingminvalueis200usandmax valueis0.5s l/r inputpinforselectingtheshiftdirectionofbid irectionalshiftregister dataisshiftedfromcomseg 119 tocomseg 0 whensettov ss level"l",anddataisshiftedfrom comseg 0 tocomseg 119 whensettov dd level"h". referto"relationshipbetweenthedisplaydataan dlcddriveoutputpins"in functionaloperations. xdispoff controlinputpinforoutputofnonselectlevel theinputsignalislevelshiftedfromlogicvolta geleveltolcddrivevoltagelevel,andcontrolst he lcddrivecircuit. whensettov ss level"l",thelcddriveoutputpins(comseg 0 comseg x )aresettolevelvss. whensetto"l,thecontentsoftheshiftregiste rareresettonotreadingdata.whenthe/ dispoff functioniscanceled,thedriveroutputsnonselect level(v 1 orv 4 ),andtheshiftdataisreadatthe nextfallingedgeofthelp.atthattime,if/disp offremovaltimedoesnotcorrespondtowhatis showninaccharacteristics,theshiftdataisnot readcorrectly. tableoftruthvaluesisshownin"truthtable"in functionaloperations. fr acsignalinputpinforlcddrivewaveform theinputsignalislevelshiftedfromlogicvolta geleveltolcddrivevoltagelevel,andcontrolst he lcddrivecircuit.
ST8012 v1.6 10/47 2004/09/08 normallyitinputsaframeinversionsignal. thelcddriveoutputpins'outputvoltagelevelsc anbesetusingtheshiftregisteroutput signaland thefrsignal. tableoftruthvaluesisshownin"truthtable"in functionaloperations. di 3 di 0 notused connectdi 3 di 0 tov ss ,notfloating. xck notused xckispulleddownincommonmode,soconnecttov ss . comseg 0 comseg 119 lcddriveoutputpins correspondingdirectlytoeachbitoftheshiftre gister,onelevel(v 0 v 1 ,v 4 ,orv ss )is selected andoutput. tableoftruthvaluesisshownin"truthtable"in functionaloperations. elo 1 ,eio 2 shiftdatainput/outputpinsforshiftregister eio 1 isoutputpinwhenl/risatvsslevell,eio 1 isinputpinwhenl/risatvddlevelh whenl/r=h,eio 1 isusedasinputpin,itwillbeconnecttoflm. whenl/r=l,eio 1 isusedasoutputpin,itwontbeconnecttoflm. eio 2 isinputpinwhenl/risatvsslevell,eio 1 isoutputpinwhenl/risatvddlevelh whenl/r=h,eio 2 isusedasoutputpin,itwontbeconnecttoflm, whenl/r=l,eio 2 isusedasinputpin,itwillbeconnecttoflm refertorelationshipbetweenthedisplaydataan dlcddriveoutputpinsin functionaloperations. cap1 dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap2terminal. cap1+ dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap1terminal. cap2 dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap2terminal. cap2+ dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap2terminal. cap3+ dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap1terminal. cap4+ dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap2terminal. cap5+ dc/dcvoltageconverter.connectacapacitor betweenthisterminalandthecap1terminal. vout dc/dcvoltageconverter.connectacapacitorb etweenthisterminalandvss. xcs this is the command mode select pin.when xcs=l t hen write command to the lcd , when not usedthecommandmodethenmustfixedtovdd.see figure1 sid thecommanddata,whennotusedthecommandmod ethenmustfixedtovdd.seefigure1 sclk theserialclockinput,whennotusedthecomm andmodethenmustfixedtovdd.seefigure1
ST8012 v1.6 11/47 2004/09/08 (common /segment mix mode) elo 1 ,eio 2 input/outputpinsforchipselection atcommon/segmentmode: whenl/rinputisatvsslevell,elo 1 issetoutput,andeio 2 issetforinput. elo 1 :segmentchipenableoutput,asdefaultsegmenti senabledinternallyandbenonselected after8,24,40,56,72or88bitsofdatahavebeenre ad.dependonselectmode. elo 2 :commonshiftdatainput,nosiftdataoutput whenl/rinputisatv dd level"h",elo 1 issetforinput,andeio 2 issetforoutput. elo 1 :commonshiftdata,noshiftdataoutput elo 2 :segmentchipenableoutput,asdefaultsegmenti senabledinternallyandbenonselected after8,24,40,56,72or88bitsofdatahavebeenre ad.dependonselectmode. duringoutput,setto"h"whilelp?xckis"h"an dafter120bitsofdatahavebeenread,set to"lforonecycle(fromfallingedgetofailing edgeofxck),afterwhichitreturnsto"h". duringinput,thechipisselectedwhileelisset to"l"afterthelpsignalisinput.thechipis nonselectedafter120bitsofdatahavebeenread.
ST8012 v1.6 12/47 2004/09/08 5.2 functional operations truth table (segmentmode) fr latch data /dispoff lcd drive output voltage lev el (comseg0-comseg119) l l h v 3 l h h v ss h l h v 2 h h h v 0 x x l v ss (commonmode) fr latch data /dispoff lcd drive output voltage lev el (comseg0-comseg119) l l h v 4 l h h v 0 h l h v 1 h h h v ss x x l v ss notes: l:v ss (0v),h:v dd (+2.5to+5.5v),x:don'tcare "don'tcare"shouldbefixedto"h"or"l",avoidi ngfloating. therearetwokindsofpowersupply(logiclevelvo ltageandlcddrivevoltage)forthelcddriver. supplyregularvoltagethatisassignedbyspecific ationforeachpowerpin.
ST8012 v1.6 13/47 2004/09/08 relationship between the display data and lcd drive output pins (segmentmode) ( a) 4-bit parallel input mode number of clocks l/r eio 1 eio 2 data input 30 clock 29 clock 28 clock 3 clock 2 clock 1 clock di 0 comseg 0 comseg 4 comseg 8 comseg 108 comseg 112 comseg 116 dl 1 comseg 1 comseg 5 comseg 9 comseg 109 comseg 113 comseg 117 di 2 comseg 2 comseg 6 comseg 10 comseg 110 comseg 114 comseg 118 l output input di 3 comseg 3 comseg 7 comseg 11 comseg 111 comseg 115 comseg 119 di 0 comseg 119 comseg 115 comseg 111 comseg 11 comseg 7 comseg 3 dl 1 comseg 118 comseg 114 comseg 110 comseg 10 comseg 6 comseg 2 di 2 comseg 117 comseg 113 comseg 109 comseg 9 comseg 5 comseg 1 h input output di 3 comseg 116 comseg 112 comseg 108 comseg 8 comseg 4 comseg 0 (b) serial input mode number of clocks l/r eio 1 eio 2 data input 120 clock 119 clock 118 clock 3 clock 2 clock 1 clock di 0 comseg 0 comseg 1 comseg 2 comseg 117 comseg 118 comseg 119 dl 1 x x x x x x x di 2 x x x x x x x l output input di 3 x x x x x x x di 0 comseg 119 comseg 118 comseg 117 comseg 2 comseg 1 comseg 0 dl 1 x x x x x x x di 2 x x x x x x x h input output di 3 x x x x x x x (commonmode) l/r data transfer direction eio 1 eio 2 l comseg 119 comseg 0 output input h comseg 0 comseg 119 input output
ST8012 v1.6 14/47 2004/09/08 mixmode(segment/commonmode) when(sel2,sel1,sel0)=(0,0,1) selectthe32com/88segmentmode thensegmentsideofmixmode (a) 4-bit parallel input mode number of clocks l/r eio 1 eio 2 data input 22 clock 21 clock 20 clock 3 clock 2 clock 1 clock di 0 comseg 0 comseg 4 comseg 8 comseg 76 comseg 80 comseg 84 dl 1 comseg 1 comseg 5 comseg 9 comseg 77 comseg 81 comseg 85 di 2 comseg 2 comseg 6 comseg 10 comseg 78 comseg 82 comseg 86 l seg_end output com_flm input di 3 comseg 3 comseg 7 comseg 11 comseg 79 comseg 83 comseg 87 di 0 comseg 119 comseg 115 comseg 110 comseg 43 comseg 39 comseg 35 dl 1 comseg 118 comseg 114 comseg 109 comseg 42 comseg 38 comseg 34 di 2 comseg 117 comseg 113 comseg 108 comseg 41 comseg 37 comseg 33 h com_flm input seg_end output di 3 comseg 116 comseg 112 comseg 107 comseg 40 comseg 36 comseg 32 (b) serial input mode number of clocks l/r eio 1 eio 2 data input 88 clock 87 clock 86 clock 3 clock 2 clock 1 clock di 0 comseg 0 comseg 1 comseg 2 comseg 85 comseg 86 comseg 87 dl 1 x x x x x x x di 2 x x x x x x x l seg_end output com_flm input di 3 x x x x x x x di 0 comseg 119 comseg 118 comseg 117 comseg 34 comseg 33 comseg 32 dl 1 x x x x x x x di 2 x x x x x x x h com_flm input seg_end output di 3 x x x x x x x commonsideofmixmode l/r data transfer direction eio 1 eio 2 l comseg 119 comseg 88 seg_endoutput input h comseg 0 comseg 31 input seg_endoutput notes: l:v ss (0v),h:v dd (+2.5to+5.5v),x:don'tcare "don'tcare"shouldbefixedto"h"or"l",avoidi ngfloating.
ST8012 v1.6 15/47 2004/09/08 connection examples of plural segment drivers (120 segment) (c) when l/r = l (d) when l/r = h comseg 0 eio2 eio2 eio2 eio1 eio1 eio1 xck lp fr di 3 di 0 xck lp fr di 3 di 0 l/r l/r l/r v dd 4 topdata lastdata data flow xck lp fr di 3 di 0 xck lp fr di 3 di 0 v ss comseg 119 comseg 0 comseg 119 comseg 0 comseg 119 eio2 eio2 eio2 eio1 eio1 eio1 xck lp fr di 3 di 0 xck lp fr di 3 di 0 xck lp fr di 3 di 0 xck lp fr di 3 di 0 l/r l/r l/r v ss 4 topdata lastdata data flow comseg 0 comseg 119 comseg 0 comseg 119 comseg 0
ST8012 v1.6 16/47 2004/09/08 timing chart of 4-device cascade connection of segm ent drivers n* n* n* n* n* 1 1 1 1 1 2 2 2 2 2 device a device b device c device d top data last data *n = 30 in 4-bit parallel input mode *n = 120 in serial input mode eo (device c) eo (device b) eo (device a) ei (device a) di3 - di0 xck lp fr
ST8012 v1.6 17/47 2004/09/08 connection examples for signal common drivers (120 common) (e) l/r = l (f) l/r = h comseg 119 eio 2 lp v ss fr xdispoff l/r lp fr first flm xdispoff xck vss eio 1 comseg 0 comseg 0 fr l/r xdispoff fr lp xdispoff first lp v dd flm xck vss eio 1 eio 2 comseg 119
ST8012 v1.6 18/47 2004/09/08 connection examples for plural common/segment (mix mode) drivers the mix mode is 1/32,1/48,1/64,1/80,1/96,1/112 duty mode (g) l/r = l (h) l/r=h y x y 0 eio1 eio2 xck lp fr v dd com seg data flow xck lp fr di 3 di 0 di3di0 flm y x+1 y 119 y 0 eio1 eio2 l/r seg xck lp fr di 3 di 0 y 119 4 l/r l/r v ss v ss pscomseg y x y 0 eio2 eio1 xck lp fr l/r v dd com seg data flow xck lp fr di 3 di 0 di3di0 flm y x+1 y 119 y 0 eio2 eio1 l/r seg xck lp fr di 3 di 0 y 119 4 pscomseg
ST8012 v1.6 19/47 2004/09/08 connection examples for 120 com &120 seg (for 1/120 duty) (i) l/r = l (j) l/r = h y x y 0 eio1 eio2 xck lp fr v dd com com data flow xck lp fr di 3 di 0 di3di0 flm y x+1 y 119 y 0 eio1 eio2 l/r seg xck lp fr di 3 di 0 y 119 4 l/r l/r v ss v ss pscomseg v ss vss y x y 0 eio2 eio1 xck lp fr l/r v dd com com data flow xck lp fr di 3 di 0 di3di0 flm y x+1 y 119 y 0 eio2 eio1 l/r seg xck lp fr di 3 di 0 y 119 4 pscomseg v ss vss
ST8012 v1.6 20/47 2004/09/08 precautions precautions when connecting or disconnecting the po wer supply thisichasahighvoltagelcddriver,soahighcu rrent that may flow if voltage is supplied to the lcd dri ve power supply while the logic system power supply is floatingmaypermanentlydamageit.thedetailsare as follows, when connecting the power supply, connect the lcd drive power after connecting the logic system power . furthermore, when disconnecting the power, disconnectthe logicsystempowerafterdisconnecti ng thelcddrivepower andwhenconnectingthelogicpowersupply,thelog ic condition of this ic inside is insecure. therefore connect the lcd drive power supply after resetting logicconditionofthisicinsideon/dispofffunct ion. afterthat,cancelthe/dispofffunctionafterthe lcd drive power supply has become stable. furthermore, when disconnecting the power, set the lcd drive output pins to level vss on /dispoff function. then disconnectthe logicsystempowerafterdisconnecti ng thelcddrivepower. when connecting the power supply, follow the recommendedsequenceshownhere v dd v ss v dd v ss v dd v ss v dd xdispoff v 0
ST8012 v1.6 21/47 2004/09/08 6. description functions the mpu interface selectingtheinterfacetype withtheST8012chips,datatransfersaredonethro ugh an4bitparalleldatabus(d3tod0)orthrougha serial datainput(si).throughselectingthep/sterminal polaritytothehorlitispossibletoselect either paralleldatainputorserialdatainputasshowni ntable 1. table 1 p/s d 0 d 3 ~d 1 h:parallelinput d 0 d 3 ~d 1 l:serialinput si vdd command serial interface withtheST8012chips,commanddatatransfersare donethroughaserialdatainput.anditstimings howin figure1. figure1 sclk xcs sid 1 2 3 4 5 10 11 12 13 14 15 1 rite command timing diagram rite command timing diagram rite command timing diagram rite command timing diagram d d d5 d4 d3 d2 d1 d0 d d d5 d4 d3 d2 d1 d0 ps :when dont use the command must set xcs to heig ht level. the power supply circuits (use serial interface) thepowersupplycircuitsarelowpowerconsumption powersupplycircuitsthatgeneratethevoltagelev els requiredforthelcddrivers.theyareboostercirc uits, voltageregulatorcircuits,andvoltagefollowerci rcuits. theyareonlyenabledinmasteroperation,whenthe modeisincommonmodeorcommon/segmentmode. thepowersupplycircuitscanturntheboostercirc uits, thevoltageregulatorcircuits,andthevoltagefol lower circuitsonoroffindependentlythroughtheuseof thepowercontrolsetcommand.consequently,itis possibletomakeanexternalpowersupplyandthe internalpowersupplyfunctionsomewhatinparallel . table3showsthepowercontrolsetcommand3bit datacontrolfunction,andtable4showsreference combinations. table3 bit function status 111 000 d2 d1 d0 boostercircuitcontrolbit on off thecontroldetailsofeachbitofthepowercontro lsetcommand
ST8012 v1.6 22/47 2004/09/08 table4 use settings com / seg d2 voltage booster voltage regulator voltage follower external voltage input step-up voltage onlytheinternalpowersupply isused 1 on on on vdd used onlythevoltageregulator circuitandthevoltage followercircuitareused com mode / com/seg mode 0 off on on vout,vdd open onlytheinternalpowersupply isused 1 on on on vdd used onlythevoltageregulator circuitandthevoltage followercircuitareused seg mode 0 off on on vout,vdd open command interface unused mode (use the default valu e) whencommandinterfaceisunused.thecs,sclkands idsignalcanbefixedasthefollowingmode table5 xcs sclk sid booster regulator follower h x x defaultregisterused(alloff) l h h off on on l l h on on on thedefaultbias,contrastcontrol,ra/rbratioandb oostfrequencyisusedwhentheabovemodeis selected. note :ifallofthecs,sclkandsidsignalsaresetto lowlevel.thedefaultpowercontrolregisterwill beused,the powercontrolofbooster,regulatorandfollowerwi llalwaysbeoff. program note: donottogglesclkorsidfromlowlevelwhilexcs signalishight. entry standby mode: entry standby must closed the a c circuit(booster) and /xdispoff also go to low level.
ST8012 v1.6 23/47 2004/09/08 the step-up voltage circuits usingthestepupvoltagecircuitsequippedwithin the ST8012chipsitispossibletoproducta2x,3x,4x ,5x or6xstepupofthev dd Cv ss voltagelevels. 6xstepup: connectcapacitorc1betweencap1+andcap1C, betweencap2+andcap2C,betweencap1+and cap3C,betweencap2+andcap4C,betweencap1+ andcap5C,andbetweenv dd andv out ,toproducea voltagelevelinthenegativedirectionatthev out terminalthatis6timesthevoltagelevelbetween v dd andv ss . 5xstepup: connectcapacitorc1betweencap1+andcap1C, betweencap2+andcap2C,betweencap1+and cap3C,betweencap2+andcap4C,andbetweenv dd andv out ,toproduceavoltagelevelinthenegative directionatthevout terminalthatis5timesthe voltagelevelbetweenv dd andv ss . 4xstepup: connectcapacitorc1betweencap1+andcap1C, betweencap2+andcap2C,betweencap1+and cap3C,andbetweenv dd andv out ,toproducea voltagelevelinthenegativedirectionatthev out terminalthatis4timesthevoltagelevelbetween v dd andv ss . 3xstepup: connectcapacitorc1betweencap1+andcap1C, betweencap2+andcap2Candbetweenv dd and v out ,andshortbetweencap3Candv out toproduce avoltagelevelinthenegativedirectionatthev out terminalthatis3timesthevoltagedifferencebet ween v dd andv ss .thestepupvoltagerelationshipsare showninfigure2. 2xstepup: connectcapacitorc1betweencap1+andcap1C, andbetweenv dd andv out ,leavecap2+open,and shortbetweencap2C,cap3Candv out to produce avoltageinthenegativedirectionatthev out terminal thatistwicethevoltagebetweenv dd andv ss .
ST8012 v1.6 24/47 2004/09/08 figure2 *thev ss voltagerangemustbesetsothatthev out terminalvoltagedoesnotexceedtheabsolutemaxi mumratedvalue. v dd v ot cap3+ cap1- cap1+ cap2+ cap2- st012 v dd v ot cap3+ cap1- cap1+ cap2+ cap2- st012 c1 c1 c1 c1 c1 c1 c1 v dd v ot cap3+ cap1- cap1+ cap2+ cap2- st012 c1 c1 open 4x step-up voltage circuit 3x step-up voltage circui t 2x step-up voltage circuit cap4+ cap5+ cap4+ cap5+ cap4+ cap5+ v dd 3v vss0v v ot 4xv dd 12v 4x step-up voltage relationsips v dd v ot cap3+ cap1- cap1+ cap2+ cap2- st012 c1 c1 c1 c1 5x step-up voltage circuit cap4+ cap5+ c1 v dd v ot cap3+ cap1- cap1+ cap2+ cap2- st012 c1 c1 c1 c1 x step-up voltage circuit cap4+ cap5+ c1 c1 3x step-up voltage relationsips 2x step-up voltage relationsips 5x step-up voltage relationsips x step-up voltage relationsips v dd 3v vss0v v ot 3xv dd v v dd 3v vss0v v ot 2xv dd v v dd 3v vss0v v ot 5xv dd 15v v dd 2.5v vss0v v ot xv dd 15v vout
ST8012 v1.6 25/47 2004/09/08 thevoltageregulatorcircuit the stepup voltage generated at v out outputs the lcd driver voltage v 0 through the voltage regulator circuit. because the st78012 chips have an internal highaccuracy fixed voltage power supply with a 64level electronic volume function and internal resistorsforthev 0 voltageregulator,systemscanbe constructed without having to include highaccuracy voltageregulatorcircuitcomponents.(vreg thermal gradientsapproximate0.05%/c) (a)whenthev 0 voltageregulatorinternalresistorsareused through the use of the v 0 voltage regulator internal resistorsandtheelectronicvolumefunctiontheli quid crystalpowersupplyvoltagev 0 canbecontrolledby commands alone (without adding any external resistors), making it possible to adjust the liquid crystal display brightness. the v 0 voltage can be calculatedusingequationa1overtherangewhere |v 0 |<|v out |. figure 3 rb ra + 1 v ev v 0 rb ra + 1 1 - 200 v reg v ev 1 - 200 v reg internal rb internal ra v ev constant voltage supply+electronic volume v 0 v ss
ST8012 v1.5 26/47 2004/04/05 vregistheicinternalfixedvoltagesupply,andi tsvoltageatta=25cisasshownintable6. table6 part no. equipment type thermal gradient v reg ST8012 internalpowersupply C0.05%/c 2.1v is set to 1 level of 64 possible levels by the el ectronic volume function depending on the data set in the 6bit electronicvolumeregister.table6showsthevalue fordependingontheelectronicvolumeregisters ettings. rb/raisthev0voltageregulatorinternalresistor ratio,andcanbesetto8differentlevelsthroug hthev0voltage regulatorinternalresistorratiosetcommand.the rb/raratioassumesthevaluesshownintable8dep endingon the3bitdatasettingsinthevddvoltageregulato rinternalresistorratioregister. table7 d5 d4 d3 d2 d1 d0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 0 : : 1 1 1 1 0 1 1 1 1 1 1 0 1 1 1 1 1 1 63 62 61 : : 2 1 0 v 0 voltageregulatorinternalresistanceratioregist ervalueand(1+rb/ra)ratio(referencevalue) table8 register ST8012 d2 d1 d0 (1)C0.05%/c 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 5.0 5.22 5.48 5.76 6.07 6.42 6.81 7.25 10 11 12 13 14 15 1 1 4 10 13 1 1 22 25 2 31 34 3 40 43 4 4 52 55 5 1 4 0 1 2 3 4 5 ta=25 andboosteroff,regulator,followeron,out=16v, vdd=3v electronicvolume resistorratiosetd2 ,d1, andd0 v0 unit :v
ST8012 v1.6 27/47 2004/09/08 the lcd voltage generator circuit thev 0 voltageisproducedbyaresistivevoltage dividerwithintheic,andcanbeproducedatthev 1 ,v 2 , v 3 ,andv 4 voltagelevelsrequiredforliquidcrystal driving.moreover,whenthevoltagefollowerchange s theimpedance,itprovidesv 1 ,v 2 ,v 3 andv 4 tothe liquidcrystaldrivecircuit. reference circuit examples figure5showsreferencecircuitexamples. 1.whenusedallofthestepupcircuit,voltage regulatingcircuitandv/fcircuit. 2.whenthevoltageregulatorcircuitandv/fcircui t aloneareused (examplewith4xsetupup) figure 4 vdd vot cap3+ cap1- cap1+ cap2- cap2+ v0 v1 v2 v3 v4 vss st012 c1 c1 c1 c1 c2 c2 c2 c2 vdd cap4+ cap5+ c2 vss vout vdd vot cap3+ cap1- cap1+ cap2- cap2+ v0 v1 v2 v3 v4 vss st012 c2 c2 c2 c2 vdd externa l power supply cap4+ cap5+ c2 vss
ST8012 v1.6 28/47 2004/09/08 3 . whenthebuiltinpowercircuitisusedtodrivea liquidcrystalpanelheavilyloadedwithacordc, itis recommendedtoconnectanexternalresistorto stabilizepotentialsofv 1 ,v 2 ,v 3 andv 4 whichare outputfromthebuiltinvoltagefollower.examples of sharedreferencesettingswhenv 0 canvary betweenC8and12v vss st012 v0 v1 v2 v3 v4 r4 r4 r4 r4 c2 vss reference set value r4:100k ~ 1m it is recommendedtosetanoptimumresistancevalue r4takingtheliquidcrystaldisplayandthedrive wveform *1.becausethevrterminalinputimpedanceishig h,useshortleadsandshieldedlines. *2.c1andc2aredeterminedbythesizeofthelc dbeingdriven.selectavaluethatwillstabilize theliquidcrystal drivevoltage. exampleoftheprocessbywhichtodeterminethese ttings: ?turnthevoltageregulatorcircuitandvoltagefo llowercircuitonandsupplyavoltagetov out fromtheoutside. ?determinec2bydisplayinganlcdpatternwitha heavyload(suchashorizontalstripes)andselecti ngac2that stabilizestheliquidcrystaldrivevoltages(v 1 tov 4 ).notethatallc2capacitorsmusthavethesamec apacitance value. ?nextturnallthepowersuppliesonanddetermine c1. item set value units c1 c2 1.0to4.7 0.1to4.7 uf uf c1andc2aredeterminedbythesizeof thelcdbeingdriven
ST8012 v1.6 29/47 2004/09/08 commands theST8012identifythedatabussignalsbyacombi nationofxcs,sdi,andsclksignals. lcd bias set thiscommandselectsthevoltagebiasratiorequire dfortheliquidcrystaldisplay. thed3canselecttheframedirection,ifselect 0isnormalelseselect1isreverse. select status d7 d6 d5 d4 d3 d2 d1 d0 1/120duty 1/112duty 1/96duty 1/80duty 1/64duty 1/48duty 1/32duty 1/11bias 1/11bias 1/10bias 1/9bias 1/9bias 1/7bias 1/6bias 0 0 0 0 0 x x 0 1 1/9bias 1/9bias 1/8bias 1/7bias 1/7bias 1/5bias 1/5bias 1/11bias 1/11bias 1/10bias 1/9bias 1/9bias 1/7bias 1/6bias 0 0 0 0 1 x x 0 1 1/9bias 1/9bias 1/8bias 1/7bias 1/7bias 1/5bias 1/5bias power controller set thiscommandsetsthepowersupplycircuitfunction s.seethefunctionexplanationinthepowersuppl ycircuit, fordetails d7 d6 d5 d4 d3 d2 d1 d0 selected mode 0 0 1 0 x 0 0 0 1 1 1 boostercircuit:off boostercircuit:on v0 voltage regulator internal resistor ratio set thiscommandsetsthev0voltageregulatorinternal resistorratio.fordetails,seethefunctionexpl anationisthe voltageregulatorcircuit"andtable7. d7 d6 d5 d4 d3 d2 d1 d0 rb/ra ratio 0 1 0 0 x 0 0 0 0 0 1 0 1 0 1 1 0 1 1 1 small large the electronic volume thiscommandmakesitpossibletoadjustthebright nessoftheliquidcrystaldisplaybycontrollingt helcddrive voltagev0throughtheoutputfromthevoltageregu latorcircuitsoftheinternalliquidcrystalpower supply. electronic volume register set byusingthiscommandtosetsixbitsofdatatoth eelectronicvolumeregister,theliquidcrystaldr ivevoltagev5 assumesoneofthe64voltagelevels.whenthiscom mandisinput,theelectronicvolumemodeisreleas edafterthe
ST8012 v1.6 30/47 2004/09/08 electronicvolumeregisterhasbeenset. d7 d6 d5 d4 d3 d2 d1 d0 |vss| 1 1 0 0 0 0 0 0 1 1 0 0 0 0 1 0 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 small large booster frequency set byusingthiscommandtosetthreebitsofdatato theboosterfrequency,theliquidcrystaldriveboo sterfrequency assumesoneofthe8frequencies.whenthiscommand isinput,theboosterfrequencyregisterhasbeen set. d7 d6 d5 d4 d3 d2 d1 d0 booster frequency 0 1 1 0 x 0 0 0 0 1 1 0 x 0 0 1 0 1 1 0 x 0 1 0 0 1 1 0 x 0 1 1 0 1 1 0 x 1 0 0 0 1 1 0 x 1 0 1 0 1 1 0 x 1 1 0 0 1 1 0 x 1 1 1 small large the default value of ST8012 whenselectcommonmodeorcommon/segmentmodethe bias contrastcontrol ra/rbratioandbooster frequencyallhavethedefaultvalue,ifuserdont notusedprogrammabletosettingthestatuscanus edthedefault value. sel3,2,1 duty bias contrastcontrol ra/rb ratio booster frequency 0,0,0 segmentmode 0,0,1 1/32 1/6 32 4 5k 0,1,0 1/48 1/7 32 4 5k 0,1,1 1/64 1/9 32 4 5k 1,0,0 1/80 1/9 32 4 5k 1,0,1 1/96 1/10 32 4 5k 1,1,0 1/112 1/11 32 4 5k 1,1,1 1/120 1/11 32 4 5k
ST8012 v1.6 31/47 2004/09/08 table of ST8012 command commandcode command d7 d6 d5 d4 d3 d2 d1 d0 function lcdbiasset 0 0 0 0 0 x x 0 1 1 d0setsthelcddrivevoltagebiasratio. 0:1/6 bias,1:1/5bias(ST8012) d3selectframedirection.0:normal,1:reverse powercontrolset 0 0 1 0 x powe rcontrolset selectinternalpowersupplyoperatingmode vssvoltageregulator internalresistorratioset 0 1 0 0 x resistor ratio selectinternalresistorratio(rb/ra)mode electronicvolumemodeset electronicvolume registerset 1 1 electronicvolumevalue setthev0outputvoltage electronicvolumeregister boosterfrequencyset 0 1 1 0 x boosterfrequency setthelcdboosterfrequency
ST8012 v1.6 32/47 2004/09/08 7. bsolute maximum ratings parameter symbol applicable pins rating unit note supplyvoltage(1) v dd v dd 0.3~+5.5 v v 1 v 1 v dd+ 10~ v dd 0.3 v 2 v 2 v dd+ 10~ v dd 0.3 v v 3 v 3 0.3~v 5s +10 v supplyvoltage(2) v 4 v 4 0.3~v 5s +10 v inputvoltage v i d1 4 di 0 ,xck,lp,l/r,fr, eio 1 ,eio 2 ,xdispoff, 0.3to v dd +0.3 v 1,2 storagetemperature t stg 45to+125 c notes: 1.ta=+25c 2.themaximumapplicablevoltageonanypinwithr especttov ss (0v). 8. recommended operating conditions parameter symbol applicable pins min. typ. max. unit note supplyvoltage(1) vdd vdd +2.5 +5.5 v supplyvoltage(2) v0 v0 +6.0 +16.0 v 1,2 operatingtemperature topr 20 +85 c
ST8012 v1.6 33/47 2004/09/08 9. electrical characteristics dc characteristics (segmentmode) (v ss =0v,v dd =+2.5to+3.6v,v 0 =+6.0to+15.0v,t opr =20to+85c) parameter symbol conditions applicable pins min. typ. max. unit note input"low"voltage v il 0.2v dd v input"high"voltage v ih di 3 di 0 ,xck,lp,l/ rfr, eio 1 ,eio 2 ,xdispoff 0.8v dd v output"low"voltage v ol i ol =+0.4ma +0.4 v output"high"voltage v oh i oh =0.4ma eio 1 ,eio 2 v dd 0.4 v i lil v i =v ss 10 a inputleakagecurrent i lih v i =v dd di 3 di 0 ,xck,lp,lir, fr,eio 1 ,eio 2 , xdispoff +10 a outputresistance r on |?v on | =0.5v v 0 =15v y 1 y 120 1.5 2.0 k standbycurrent i stb v ss 5 a 1 supplycurrent(1) (nonselection) i dd1 v dd 2.0 ma 2 supplycurrent(2) (selection) i dd2 v dd 7.0 ma 3 supplycurrent(3) i 0 v 0 ,v 0 0.9 ma 4 notes: 1.v dd =+3.0v,v 0 =+12.0v 2.v dd =+3.0v,v 0 =+12.0v,f xck =8mhz,noload,el=v dd .theinputdataisturnedoverbydatatakingcloc k(4bit parallelinputmode). 3.v dd =+3.0v,v 0 =+12.0v,f xck =8mhz,noload,el=v ss .theinputdataisturnedoverbydatatakingcloc k(4bit parallelinputmode). 4.v dd =+3.0v,v 0 =+12.0v,f xck =8mhz,f lp =19.2khz,f fr =80hz,noload.theinputdataisturnedoverby data takingclock(4bitparallelinputmode). (commonmode) (v ss =0v,v dd =+2.5to+3.6v,v 0 =+6.0to+15.0v,t opr =20to+85c) parameter symbol conditions applicabl e pins min. typ. max. unit note input"low"voltage v il 0.2v dd v input"high"voltage v ih di 4 di 0 ,xck,lp,l/ r fr,p/s,dix,eio 1 , eio 2 ,xdispoff 0.8v dd v output"low"voltage v ol i ol =+0.4ma +0.4 v output"high"voltage v oh i oh =0.4ma eio 1 ,eio 2 v dd 0.4 v i lil v i =v ss di 4 di 0 ,xck,lp,l/ r fr,p/s,dix,eio 1 , eio 2 ,xdispoff 10.0 a inputleakagecurrent i lih v i =v dd di 4 di 0 ,lp,l/r,fr, p/s,dix,xdispoff +10.0 a inputpulldowncurrent i pd v i =v dd xck,eio 1 ,eio 2 100 a outputresistance r on |?v on | =0.5v v 0 =15v comseg 0 comseg 119 1.5 2.0 k standbycurrent i spd v ss 5 a 1 supplycurrent(1) i dd v dd 80 a 2 supplycurrent(2) i 0 v o 130 a 2 notes: 1.v dd =+3.0v,v 0 =+12.0v, 2.v dd =+3.0v,v 0 =+12.0v,f lp =19.2khz,f fr =80hz,1/240dutyoperation,noload.
ST8012 v1.6 34/47 2004/09/08 ac characteristics (segmentmode1) (v ss =0v,v dd =+2.5to+3.6v,v 0 =+6.0to+15.0v,t opr =2010+85c) parameter symbol conditions min typ. max. unit note shiftclockperiod t wck t r ,t f 11ns 125 ns 1 shiftclock"h"pulsewidth t wckh 51 ns shiftclock"l"pulsewidth t wckl 51 ns datasetuptime t ds 30 ns dataholdtime t dh 40 ns latchpulse"h"pulsewidth t wlph 51 ns shiftclockrisetolatchpulserisetime t ld 0 ns shiftclockfalltolatchpulsefalltime t sl 51 ns latchpulserisetoshiftclockrisetime t ls 51 ns latchpulsefalltoshiftclockfalltime t lh 51 ns latchpulsefalltoshiftclockrisetime t lsw 50 ns enablesetuptime t s 36 ns inputsignalrisetime t r 50 ns 2 inputsignalfalltime t f 50 ns 2 dispoffremovaltime t sd 100 ns dispoff"l"pulsewidth t wdl 1.2 s outputdelaytime(1) t d cl=15pf 78 ns outputdelaytime(2) t pd1 ,t pd2 cl=15pf 1.2 s outputdelaytime(3) t pd3 cl=15pf 1.2 s notes: 1.takesthecascadeconnectionintoconsideration . 2.(t wck t wckh t wckl )/2ismaximuminthecaseofhighspeedoperation. (segmentmode2) (v ss =0v,v dd =+5.00.5v,v 0 =+6.0to+15.0v,t opr =20to+85c) parameter symb ol conditions min. typ. max. unit note shiftclockperiod t wck t r ,t f 10ns 66 ns 1 shiftclock"h"pulsewidth t wckh 23 ns shiftclock"lpulsewidth t wckl 23 ns datasetuptime t ds 15 ns dataholdtime t dh 23 ns latchpulse"h"pulsewidth t wlph 30 ns shiftclockrisetolatchpulserisetime t ld 0 ns shiftclockfalltolatchpulsefalltime t sl 50 ns latchpulserisetoshiftclockrisetime t ls 30 ns latchpulsefalltoshiftclockfalltime t lh 30 ns latchpulsefalltoshiftclockrisetime t lsw 50 ns enablesetuptime t s 15 ns inputsignalrisetime t r 50 ns 2 inputsignalfalltime t f 50 ns 2 dispoffremovaltime t sd 100 ns dispoff"l"pulsewidth t wdl 1.2 s outputdelaytime(1) t d cl=15pf 41 ns outputdelaytime(2) t pd1 ,t pd2 cl=15pf 1.2 s outputdelaytime(3) t pd3 cl=15pf 1.2 s notes: 1.takesthecascadeconnectionintoconsideration . 2.(t wck t wckh t wckl )/2ismaximuminthecaseofhighspeedoperation.
ST8012 v1.6 35/47 2004/09/08 (segmentmode3) (v ss =0v,v dd =+3.0to+3.6v,v 0 =+6.0to+15.0v,t opr =2010+85c) parameter symbol conditions min. typ. max. unit note shiftclockperiod t wck t r ,t f 10ns 82 ns 1 shiftclock"h"pulsewidth t wckh 28 ns shiftclock"lpulsewidth t wckl 28 ns datasetuptime t ds 20 ns dataholdtime t dh 23 ns latchpulse"h"pulsewidth t wlph 30 ns shiftclockrisetolatchpulserisetime t ld 0 ns shiftclockfalltolatchpulsefalltime t sl 51 ns latchpulserisetoshiftclockrisetime t ls 30 ns latchpulsefalltoshiftclockfalltime t lh 30 ns latchpulsefalltoshiftclockrisetime t lsw 50 ns enablesetuptime t s 15 ns inputsignalrisetime t r 50 ns 2 inputsignalfalltime t f 50 ns 2 dispoffremovaltime t sd 100 ns dispoff"l"pulsewidth t wdl 1.2 s outputdelaytime(1) t d cl=15pf 57 ns outputdelaytime(2) t pd1 ,t pd2 cl=15pf 1.2 s outputdelaytime(3) t pd3 cl=15pf 1.2 s notes: 1.takesthecascadeconnectionintoconsideration . 2.(t wck t wckh t wckl )/2ismaximuminthecaseofhighspeedoperation. (commonmode) (v ss =0v,v dd =+2.5to+5.5v,v 0 =+6.0to+15.0v,t opr =2010+85c) parameter symbol conditions min typ max unit shiftclockperiod t wlp t r ,t f 20ns 250 ns shiftclockhpulsewidth t wlph v dd =50.5v v dd =2.5~4.5v 15 30 ns datasetuptime t su 30 ns dataholdtime t h 50 ns inputsignalrisetime t r 50 ns inputsignalfalltime t f 50 ns dispoffremovaltime t sd 100 ns dispofflpulsewidth t wdl 1.2 us outputdelaytime(1) t dl cl=10pf 200 ns outputdelaytime(2) t pd1 ,t pd2 cl=10pf 1.2 us outputdelaytime(3) t pd3 cl=10pf 1.2 us
ST8012 v1.6 36/47 2004/09/08 timing chart of segment mode fr lp xdispoff y 1 y 120 t pd1 t pd3 t pd2 fig.8timingcharacteristics(3) lp xck di4di0 xdispoff t wlph t ld t sl t lh t ls t wckh t f t r t wck t ds t dh topdata lastdata t wdl t sd t wckl
ST8012 v1.6 37/47 2004/09/08 (commonmode) (v ss =0v,v dd =+2.5to+3.6v,v 0 =+6.0to+15.0vv,t opr =20to+85c) parameter symbol conditions min. typ. max. unit shiftclockperiod t wlp t r ,t f 20ns 250 ns v dd =+5.00.5v 15 ns shiftclock"h"pulsewidth t wlph v dd =+2.5+4.5v 30 ns datasetuptime t su 30 ns dataholdtime t h 50 ns inputsignalrisetime t r 50 ns inputsignalfalltime t f 50 ns dispoffremovaltime t sd 100 ns dispoff"l"pulsewidth t wdl 1.2 s outputdelaytime(1) t dl cl=15pf 200 ns outputdelaytime(2) t pd1 ,t pd2 cl=15pf 1.2 s outputdelaytime(3) t pd3 cl=15pf 1.2 s timing chart of common mode lp eio 2 eio 1 xdispoff t wdl t sd t dl t h t su t wlp t r t wlph t f fr lp y 1 y 120 t pd1 t pd3 t pd2 xdispoff
ST8012 v1.6 38/47 2004/09/08 theserialinterfacetiming t csh cs1 cs21 sid sclk t ccss t scc t sl t sh t sdh t sds t f t r rating item signal symbol condition min. max. units serialclockperiod tscyc 50 sclhpulsewidth tshw 25 scllpulsewidth sclk tslw 25 datasetuptime tsds 20 dataholdtime sid tsdh 10 csscltime tcss 20 csscltime cs tcsh 40 ns rating item signal symbol condition min. max. units serialclockperiod tscyc 100 sclhpulsewidth tshw 50 scllpulsewidth sclk tslw 50 datasetuptime tsds 30 dataholdtime sid tsdh 20 csscltime tcss 30 csscltime cs tcsh 60 ns rating item signal symbol condition min. max. units serialclockperiod tscyc 200 sclhpulsewidth tshw 80 scllpulsewidth sclk tslw 80 datasetuptime tsds 60 dataholdtime sid tsdh 30 csscltime tcss 40 csscltime cs tcsh 100 ns
ST8012 v1.6 39/47 2004/09/08 10. application circuit 8051 serial transfer mode example clr cs clrsclk ;sid=d.7 movbitsid,d.7 ;readdatafromsid setbsclk clrsclk ;sid=d.6 movbitsid,d.6 ;readdatafromsid setbsclk clrsclk ;sid=d.5 movbitsid,d.5 ;readdatafromsid setbsclk clrsclk ;sid=d.4 movbitsid,d.4 ;readdatafromsid setbsclk clrsclk ;sid=d.3 movbitsid,d.3 ;readdatafromsid setbsclk clrsclk ;sid=d.2 movbitsid,d.2 ;readdatafromsid setbsclk clrsclk ;sid=d.1 movbitsid,d.1 ;readdatafromsid setbsclk clrsclk ;sid=d.0 movbitsid,d.0 ;readdatafromsid setbsclk clrsclk setbcs ret
ST8012 v1.6 40/47 2004/09/08 application for data writing of segment mode whenST8012isasasegmentmodedriver,youmust write0datatothepartofnodisplay,whensegm entsarenot allused.example:thesecondsegmenthave120seg ments,butonlyuse100segmentsthenyoumustwrit e100 datathatyouneedandright,thenyoustillwrite 20 0datatofillthepartofsegmentsnotused .otherwisetherewill behaving errors,whenyoudontwritethe200 datatofillthepartofnodisplaysegments. asummaryofST8012insegmentmodeyoumustwrite thenumberofsegmentsdatatofillthesegments.(e x:use twoST8012toshowthe64x132,thenyoumustwrite the80x160datatofillthesegments,usethreest8 012to show120x200theyoumustwritethe120x240datato fillthesegments ) ex: r i t e 4 4 0 d a t a the 44 segments is not use but must write 44 0 data.
ST8012 v1.6 41/47 2004/09/08 application1 circuit for module of vlcd no duty vlcd (v) 1 1/32 6,7 2 1/48 7,8 3 1/64 9,10 4 1/80 10,11 5 1/96 10,11 6 1/112 11,12 7 1/120 11,12 note:thevalueofpanelsitoresistoris10 . application timing block: example160x80 frameandlpfallingedge(orrising edge)must>10ns betweenlpfallingedgeandxckrisingedgemust>5 0ns
ST8012 v1.5 42/47 2004/04/05 parallel vs. serial interface diagram s1 s2 s3 s4 s5 s6 s7 s8 s1 s1 s1 s1 1 5 9 13 2 6 10 14 3 7 11 15 4 8 12 16 lp d3 d2 d1 d0 1 2 3 4 5 6 7 8 15 15 15 16 14 14 15 15 14 15 15 15 14 15 15 15 14 15 15 16 1 5 9 2 6 10 3 7 11 4 8 12 d0 1 2 3 4 5 6 7 8 15 15 15 16
ST8012 v1.5 43/47 2004/04/05 application2 circuit for module 1/120 duty, 120 commons and 120 segments 120 x 120 dot lcd panel v dd di3~di0 4 v dd xdispoff v dd xck fr lp comseg 0 ~ comseg 11 di 3 ~di 0 sel 2 sel 1 sel 0 p/s xdispoff l/r xck fr lp eio 1 eio 2 st012 d i 3 ~ d i 0 s e l 2 s e l 1 s e l 0 p / s x d i s p o f f l / r x c k f r l p e i o 1 e i o 2 s t 0 1 2 comseg 0 ~ comseg 11 v dd flm v ss v ss v ss vout v0 v1 v2 v3 v4 vdd v o u t v 0 v 1 v 2 v 3 v 4 r100~3.3k 1/80 duty, 80 commons and 160 segments 0 x 10 dot lcd panel v dd di3~di0 4 v ss xdispoff v dd xck fr lp comseg 0 ~ comseg 11 di 3 ~di 0 sel 2 sel 1 sel 0 p/s xdispoff l/r xck fr lp eio 1 eio 2 st012 d i 3 ~ d i 0 s e l 2 s e l 1 s e l 0 p / s x d i s p o f f l / r x c k f r l p e i o 1 e i o 2 s t 0 1 2 comseg 0 ~ comseg 11 v dd v dd flm v ss v0 v1 v2 v3 v4 vdd v o u t v 0 v 1 v 2 v 3 v 4 r100~3.3k
ST8012 v1.6 44/47 2004/09/08 11. pad diagram chipsize 5,840(m)x2,820(m) padsize 80mx80m origin chipcenter(0,0) pinpitch 110~110m chipthickness 19mil(19x25.4m=482.6m) 1 2 11 12 13 14 15 1 1 1 1 20 21 22 23 24 25 2 2 2 2 30 31 32 33 34 35 3 3 3 3 40 41 42 43 44 54 131 132 comseg comseg110 c o m s e g 1 1 1 10 c o m s e g 1 1 c o m s e g c o m s e g 3 3 55 comseg32 comseg10 c o m s e g 0 c o m s e g v o t c a p 3 p c a p 1 n c a p 1 p c a p 2 p c a p 2 n c a p 4 p c a p 5 p v 0 v 1 v 2 v 3 v 4 x r s t d i 3 d i 2 d i 1 d i 0 e i o 1 e i o 2 x c k x d i s p o f f c s s i d s c l k f r l p v s s s e l 2 s e l 1 s e l 0 l r p s st012 45 v d d substrate connect to vss.
ST8012 v1.6 45/47 2004/09/08 unit um pin.no page pin name x y pin.no page pin name x y 1 comseg110 2810 1300 78 comseg33 2810 1300 2 comseg111 2650 1300 79 comseg34 2650 1300 3 comseg112 2510 1300 80 comseg35 2510 1300 4 comseg113 2380 1300 81 com seg36 2380 1300 5 comseg114 2260 1300 82 comseg37 2260 1300 6 comseg115 2150 1300 83 comseg38 2150 1300 7 comseg116 2050 1300 84 comseg39 2050 1300 8 comseg117 1950 1300 85 comseg40 1950 1300 9 comseg118 1850 1300 86 comseg41 1850 1300 10 comseg119 1750 1300 87 comseg42 1750 1300 11 vout 1650 1300 88 comseg43 1650 1300 12 cap3p 1550 1300 89 comseg44 1550 1300 13 cap1n 1450 1300 90 comseg45 1450 1300 14 cap1p 1350 1300 91 comseg46 1350 1300 15 cap2p 1250 1300 92 comseg47 1250 1300 16 cap2n 1150 1300 93 comseg48 1150 1300 17 cap4p 1050 1300 94 comseg49 1050 1300 18 cap5p 950 1300 95 comseg50 950 1300 19 v0 850 1300 96 comseg51 850 1300 20 v1 750 1300 97 comseg52 750 1300 21 v2 650 1300 98 comseg53 650 1300 22 v3 550 1300 99 comseg54 550 1300 23 v4 450 1300 100 comseg55 450 1300 24 xrst 350 1300 101 comseg56 350 1300 25 di3 250 1300 102 comseg57 250 1300 26 di2 150 1300 103 comseg58 150 1300 27 di1 5 0 1300 104 comseg59 50 1300 28 di0 50 1300 105 comseg60 50 1300 29 eio1 150 1300 106 comseg61 150 1300 30 eio2 250 1300 107 comseg62 250 1300 31 xck 350 1300 108 comseg63 350 1300 32 xdispoff 450 1300 109 comseg64 450 1300 33 xcs 550 1300 110 comseg65 550 1300 34 sid 650 1300 111 comseg66 650 1300 35 sclk 750 1300 112 comseg67 750 1300 36 fr 850 1300 113 comseg68 850 1300 37 lp 950 1300 114 comseg69 950 1300 38 vss 1050 1300 115 comseg70 1050 1300 3 9 sel2 1150 1300 116 comseg71 1150 1300 40 sel1 1250 1300 117 comseg72 1250 1300 41 sel0 1350 1300 118 comseg73 1350 1300 42 lr 1450 1300 119 comseg74 1450 1300 43 ps 1550 1300 120 comseg75 1550 1300 44 vdd 1650 1300 121 comseg7 6 1650 1300 45 comseg0 1750 1300 122 comseg77 1750 1300 46 comseg1 1850 1300 123 comseg78 1850 1300
ST8012 v1.6 46/47 2004/09/08 47 comseg2 1950 1300 124 comseg79 1950 1300 48 comseg3 2050 1300 125 comseg80 2050 1300 49 comseg4 2150 1300 126 comseg81 2150 130 0 50 comseg5 2260 1300 127 comseg82 2260 1300 51 comseg6 2380 1300 128 comseg83 2380 1300 52 comseg7 2510 1300 129 comseg84 2510 1300 53 comseg8 2650 1300 130 comseg85 2650 1300 54 comseg9 2810 1300 131 comseg86 2810 1300 55 coms eg10 2810 1160 132 comseg87 2810 1160 56 comseg11 2810 1030 133 comseg88 2810 1030 57 comseg12 2810 910 134 comseg89 2810 910 58 comseg13 2810 800 135 comseg90 2810 800 59 comseg14 2810 700 136 comseg91 2810 700 60 comseg15 2810 6 00 137 comseg92 2810 600 61 comseg16 2810 500 138 comseg93 2810 500 62 comseg17 2810 400 139 comseg94 2810 400 63 comseg18 2810 300 140 comseg95 2810 300 64 comseg19 2810 200 141 comseg96 2810 200 65 comseg20 2810 100 142 comseg97 2810 100 66 comseg21 2810 0 143 comseg98 2810 0 67 comseg22 2810 100 144 comseg99 2810 100 68 comseg23 2810 200 145 comseg100 2810 200 69 comseg24 2810 300 146 comseg101 2810 300 70 comseg25 2810 400 147 comseg102 2810 400 71 co mseg26 2810 500 148 comseg103 2810 500 72 comseg27 2810 600 149 comseg104 2810 600 73 comseg28 2810 700 150 comseg105 2810 700 74 comseg29 2810 800 151 comseg106 2810 800 75 comseg30 2810 910 152 comseg107 2810 910 76 comseg31 281 0 1030 153 comseg108 2810 1030 77 comseg32 2810 1160 154 comseg109 2810 1160
ST8012 v1.6 47/47 2004/09/08 note 2001.12/19modifytheboostercapacity 20021/8modifytheserialcommandinterfacetiming block(p16) 20021/14modifytheregistercommandcode 20021/17modifytheresetregistercommanddefined 20021/23modifythepindescriptiondefinedandco mmandinterfaceunusedmode(p17) 20022/22modifytheboostercircuitdiagram(p19) 20022/22modifythemixmodetable(p10) addtheserialinterfacetiming(p33 p34) addpad data(p37) 20022/22modifythecsset(p34) 2002/3/20modifytheserialinterface,wheninthe serialinterfacethed0 ? data.andaddtheac direction. 2002/4/3modifythepadlocation(p39) 2002/06/04modifythexrestactive(p2) 2002/06/010modifythechipsize(p37) 2002/06/21modifycommonandsegmentmodepindescr iption(p6~p8) 2002/07/01modifyboostercircuit(p20) 2002/07/09commandinterfaceunusedmode(usethed efaultvalue)(p18) 2002/10/14deletethesoftwareresetandcogpackag e,addtheregulatorlinerline,deletesome acapplication. 2002/11/22modifytheboosterfrequencyv1.1a 2003/03/31modifyboosterturnsoffcommand(p28) 2003/04/04addthexcsusedmath. 2003/4/17modifytheapplicationcircuit 2003/6/17addapplicationcircuitv1.3 2003/11/12addpinpitchvaluev1.4 2004/04/05addapplicationtimingblockv1.5 2004/09/08definetiming( t lsw )ofsegmentmode.p33~p35v1.6 the above information is the exclusive intellectual property of sitronix technology corp. and shall no t be disclosed, distributed or reproduced without permissionfromsitronix.

▲Up To Search▲

Price & Availability of ST8012

	To Download ST8012 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .